Test pattern for measuring contact resistance and method of manufacturing the same

ABSTRACT

The present invention relates to a test pattern for measuring a contact resistance and method of manufacturing the same. In order to confirm that a contact resistance suitable for a semiconductor device before an actual process for manufacturing the device is performed, the present invention designs a test pattern for measuring the contact resistance depending on a design rule of a line contact actually applied to an actual device. At this time, a first line contact region and a second line contact region are formed between a word line so that a line contact region can form a pair; a plurality of sources are formed in the first line contact region and a plurality of sources are formed in the second line contact region wherein neighboring sources are connected by diffusion layers so that the first line contact region and the second line contact region can be electrically connected; and a plurality of line contact patterns are formed so that the plurality of the sources can be electrically connected by every two in each of the first and second line contact regions wherein the line contact pattern formed in the first line contact region and the line contact pattern formed in the second line contact region are alternately positioned. Therefore, the present invention can allow current for measuring the resistance sequentially along the first line contact region and the second line contact region to measure the line contact resistance in which the contact resistance in every source portion is considered.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates generally to a test pattern for measuring acontact resistance and method of manufacturing the same, and moreparticularly to, a test pattern for measuring a contact resistance andmethod of manufacturing the same, capable of easily measuring a contactresistance in a semiconductor device using a self-aligned line contact.

[0003] 2. Description of the Prior Art

[0004] In general, as the integration level of semiconductor devices,the contact area becomes narrow. As the contact are is narrowed, thereis a problem that the contact resistance is increased due to defectivecontact. Therefore, in order to confirm that the contact resistancesuitable for the semiconductor device before an actual process formanufacturing the device is performed, a test pattern for measuring acontact resistance is manufactured depending on a design rule of acontact actually applied to a device and the contact resistance ismeasured using the manufactured test pattern for measuring a contactresistance.

[0005]FIG. 1 is a structure of a test pattern for measuring aconventional contact resistance.

[0006] Referring now to FIG. 1, a plurality of device isolation films 12are formed in a test wafer 11 to define a plurality of active regions.After word lines (not shown) are formed, a plurality of source/draindiffusion layers 13 are formed by source/drain ion implantation process.An interlayer insulating film (not shown) and a contact hole (not shown)are formed on the entire structure in which the plurality of thesource/drain diffusion layers 13 are formed. A contact pattern 14 isformed within the contact hole. Two contact patterns 14 are formed inevery source/drain diffusion layer 13. Then, an interconnection pattern15 for electrically connecting the plurality of the source/draindiffusion layers 13 is formed.

[0007] A series of a process of manufacturing a test pattern formeasuring a contact resistance is performed based on a design rule of aprocess of manufacturing an actual device.

[0008] As shown in FIG. 1, in the conventional test pattern formeasuring a contact resistance, two isolated contact patterns 14 areformed in a single isolated source/drain diffusion layer 13 and theinterconnection pattern 15 is formed in the two contact patterns 14,respectively, so that it can be connected to neighboring another contactpattern 14. A flow of current necessary to measure the contactresistance has a two-dimensional current flow in order of theinterconnection pattern 15, the contact pattern 14 and the source/draindiffusion layer 13, as a current path 16 shown in FIG. 1.

[0009] An ideal total resistance, when the contact pattern 14 preferablycontacts the source/drain diffusion layer 13, can be easily found by ageneral mathematic equation. If the total resistance obtained by thetest pattern for measuring a contact resistance is similar to the idealtotal resistance, a design rule for manufacturing an actual device isapplied. If the total resistance obtained by the test pattern formeasuring a contact resistance is higher than the ideal totalresistance, it is assumed that a defective contact is generated. Thus, anew design rule is applied or another solution is considered. As such,defective devices can be prevented in advance and unnecessary time andcost could be reduced, by allowing the test pattern for measuring acontact resistance to in advance diagnose a possible problem that can begenerated in an actual device.

[0010] Recently, a semiconductor device using a self-aligned linecontact is formed. However, the contact resistance of the semiconductordevice could not be measured using the conventional test pattern formeasuring a contact resistance. In other words, the conventional testpattern for measuring a contact resistance is suitable to measure thecontact resistance of the device having an isolated source/draindiffusion layer and an isolated contact pattern but is not suitable tomeasure the contact resistance of a device having a self-aligned linecontact.

[0011] A flash EEPROM as a semiconductor device using the self-alignedline contact will be below described as an example. A plurality ofdevice isolation films are first formed to define a plurality of activeregions. Word lines surrounded by a spacer insulating film are thenformed and a source/drain diffusion layer is formed. Next, an interlayerinsulating film is then deposited and flattened. A self-aligned contacthole through which the plurality of the source diffusion layers areexposed is formed by a self-aligned source contact process and theself-aligned contact is filled with a conductive layer to form a sourceline contact.

[0012] As such, the source line contact connects the plurality of thesource diffusion layers into one. Therefore, if a two-dimensionalcurrent flow is generated as in a prior art, current flows along theline contact made of a conductive material of a low resistance butcurrent does not flow into the source diffusion layer formed by ionimplantation process. Thus, it could not be seen that defective contactoccurred in respective source diffusion layers.

[0013] Considering advantages that allows the test pattern for measuringa contact resistance to diagnose in advance problems generated in anactual device to prevent defective devices in advance and to reduceunnecessary time and cost, there is a need for a test pattern formeasuring a contact resistance suitable for a semiconductor device usingthe self-aligned line contact.

SUMMARY OF THE INVENTION

[0014] The present invention is contrived to solve the above problemsand an object of the present invention is to provide a test pattern formeasuring a contact resistance and method of manufacturing the same,capable of easily measuring a contact resistance in a semiconductordevice using a self-aligned line contact.

[0015] In order to accomplish the above object, a test pattern formeasuring a contact resistance according to the present invention, ischaracterized in that it comprises a test wafer in which a plurality ofdevice isolation films are formed to define a plurality of activeregions; a plurality of interconnection diffusion layer formed in a wordline region crossing the plurality of the device isolation films and theplurality of the active regions; a plurality of source diffusion layersformed in a first line contact region located at one side of the wordline region; a plurality of source diffusion layers formed in a secondline contact region located at the other side of the word line region;and a plurality of line contact pattern formed in the first and secondline contact regions, wherein the line contact pattern formed in thefirst line contact region and the line contact pattern formed in thesecond line contact region are alternately positioned and whereincurrent for measuring a resistance flows along the first line contactregion and the second line contact region between the word line in athree-dimensional manner.

[0016] A method of manufacturing a test pattern for measuring a contactresistance according to the present invention, is characterized in thatit comprises the steps of forming a plurality of device isolation filmsin a test wager to define a plurality of active regions; performing animpurity ion implantation process to simultaneously form a sourcediffusion layer in a plurality of active regions of a first line contactregion, an interconnection diffusion layer in a plurality of activeregions of a word line and a source diffusion layer in a plurality ofactive regions of a second line contact region; forming a word linesurrounded by an insulating film spacer in the word line region; formingan insulating layer the surface of which is flattened on the entirestructure including the word line; forming a self-aligned contact maskon the insulating layer; and forming a plurality of line contactpatterns in the first and second line contact regions through aself-aligned contact process using the self-aligned contact mask,wherein the line contact pattern formed in the first line contact regionand the line contact pattern formed in the second line contact regionare alternately positioned and current for measuring a resistance flowsalong the first line contact region and the second line contact regionbetween the word line in a three-dimensional manner.

[0017] Further, a method of manufacturing a test pattern for measuring acontact resistance according to the present invention, is characterizedin that it comprises the steps of forming a plurality of deviceisolation films in a test wafer to define a plurality of active regions;performing a threshold voltage ion implantation process to form athreshold voltage ion implantation region in the plurality of the activeregions in a word line region; forming a word line in the word lineregion; performing an impurity ion implantation process to form a sourcediffusion layer in each of the plurality of the active regions of afirst line contact region and a source diffusion layer in each of theplurality of the active regions of a second line contact region; formingan insulating film spacer surrounding the word line; forming aninsulating layer the surface of which is flattened on the entirestructure including the word line; forming a self-aligned contact maskon the insulating layer; and forming a plurality of line contactpatterns in the first and second line contact regions through aself-aligned contact process using the self-aligned contact mask,wherein the line contact pattern formed in the first line contact regionand the line contact pattern formed in the second line contact regionare alternately positioned and current for measuring a resistance flowsalong the first line contact region and the second line contact regionbetween the word line in a three-dimensional manner.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The aforementioned aspects and other features of the presentinvention will be explained in the following description, taken inconjunction with the accompanying drawings, wherein:

[0019]FIG. 1 is a structure of a test pattern for measuring aconventional contact resistance;

[0020]FIG. 2 is a structure of a test pattern for measuring a contactresistance according to the present invention;

[0021]FIG. 3˜FIG. 5 are cross sectional views for describing a method ofmanufacturing a test pattern for measuring a contact resistance in FIG.2 according to a first embodiment of the present invention; and

[0022]FIG. 6˜FIG. 8 are cross sectional views for describing a method ofmanufacturing a test pattern for measuring a contact resistance in FIG.2 according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0023] The present invention will be described in detail by way of apreferred embodiment with reference to accompanying drawings, in whichlike reference numerals are used to identify the same or similar parts.

[0024]FIG. 2 is a structure of a test pattern for measuring a contactresistance according to the present invention.

[0025] As can be seen from FIG. 2, the test pattern for measuring acontact resistance of the present invention includes a plurality ofdevice isolation films 30 on a test wafer 20 to define a plurality ofactive regions 40; a plurality of interconnection diffusion layers 61 a,61 b or 61 c in word line regions 60 crossing the plurality of thedevice isolation films 30 and a plurality of active regions; a pluralityof source diffusion layers 51 a, 51 b and 51 c in a first line contactregion 50 located at one side of the word line regions 60; a pluralityof source diffusion layers 71 a, 71 b and 71 c in a second line contactregion 70 located at the other side of the word line regions 60; aplurality of line contact patterns 500 a and 500 b in the first linecontact region 50; and a plurality of line contact patterns 700 a and700 b in the second line contact region 70. A current path 567 isconstructed to form a three-dimensional flow of current including thefirst line contact pattern 500 a in the first line contact region 50, afirst source diffusion layer 51 in the first line contact region 50, theinterconnection diffusion layer 61 a in the word line region 60, thefirst source diffusion layer 71 a in the second line contact region 70,a first line contact pattern 700 a in the second line contact region 70,and the second source diffusion layer 71 b in the second line contactregion 70.

[0026] In the above, the source diffusion layers 51 a/71 a or 51 b/71 bor 51 c/71 c neighboring to the first line contact region 50 and thesecond line contact region 70 are electrically connected by theinterconnection diffusion layers 61 a, 61 b or 61 c in the word lineregion 60. Each of the plurality of the line contact patterns 500 a, 500b, 700 a and 700 b formed in the first and second line contact regions50 and 70 are isolated/positioned so that they can be electricallyconnected to only every two source diffusion layers 51 b/51 c or 71 a/71b. Also, the line contact patterns 500 a and 500 b formed in the firstline contact region 50 and the line contact patterns 700 a and 700 bformed in the second line contact region 70 are alternately positioned.

[0027] In the test pattern for measuring a contact resistance of thepresent invention, current for measuring the resistance can flow alongthe first line contact region 50 and the second line contact region 70,in a three-dimension manner, as in the current path 567 shown in FIG. 2.Therefore, a line contact resistance can be measured considering thecontact resistance at the source diffusion layers 51 a, 51 b, 51 c, 71a, 71 b or 71 c portion.

[0028] A method of manufacturing the test pattern for measuring acontact resistance for use in a semiconductor device using theself-aligned line contact will be below described by reference to FIG.3˜FIG. 5 and FIG. 6˜FIG. 8.

[0029]FIG. 3˜FIG. 5 are cross sectional views for describing a method ofmanufacturing a test pattern for measuring a contact resistance in FIG.2 according to a first embodiment of the present invention, wherein FIG.3a, FIG. 4a and FIG. 5a illustrates a layout; FIG. 3b, FIG. 4b and FIG.5b are cross sectional views of the test pattern taken along lines B-Bin FIG. 3a, FIG. 4a and FIG. 5a, respectively; FIG. 3c, FIG. 4c and FIG.5c are cross-sectional views of the test pattern taken along lines C-Cin FIG. 3a, FIG. 4a and FIG. 5a, respectively; and FIG. 3d, FIG. 4d andFIG. 5d are cross-sectional views of the test pattern taken along linesD-D in FIG. 3a, FIG. 4a and FIG. 5a, respectively.

[0030] Referring now to FIG. 3, the plurality of the device isolationfilms 30 are formed in the test wafer 20 to define the plurality ofactive regions 40. The first line contact region 50 and the second linecontact region 70 are defined so that a pair of the line contact regionscan be formed between the word line region 60. An impurity implantationprocess is implemented to form the source diffusion layers 51 a, 51 band 51 c in each of the plurality of the active regions 40 of the firstline contact region 50, the interconnection diffusion layers 61 a, 61 band 61 c in each of the plurality of the active regions 40 of the wordline region 60 and the source diffusion layers 71 a, 71 b and 71 c ineach of the plurality of the active region 40 of the second line contactregion 70, at the same time.

[0031] In the above, the first line contact region 50 and the secondline contact region 70 are electrically connected by the plurality ofinterconnection diffusion layers 61 a, 61 b and 61 c. More particularly,the first source diffusion layers 51 a and 71 a in the first and secondline contact regions 50 and 70 are electrically connected by the firstinterconnection diffusion layer 61 a in the word line region 60, thesecond source diffusion layers 51 b and 71 b in the first and secondline contact regions 50 and 70 are electrically connected by the secondinterconnection diffusion layer 61 b in the word line region 60, and thethird source diffusion layers 51 c and 71 c in the first and second linecontact regions 50 and 70 are electrically connected by the thirdinterconnection diffusion layer 61 c in the word line region 60.

[0032] Referring now to FIG. 4, the word line 61 surrounded by aninsulating film spacer 80 is formed in the word line region 60. Aninsulating layer 90 the surface of which is flattened is formed on theentire structure including the word line 61. A self-aligned contact mask100 is formed on the insulating layer 90.

[0033] In the above, the self-aligned contact mask 100 is formed tocover an upper portion of the word line 61, an upper portion of aportion of the device isolation film 30 between the first sourcediffusion layer 51 a and the second source diffusion layer 51 b in thefirst line contact region 50, and an upper portion of a portion of thedevice isolation film 30 between the second source diffusion layer 71 band the third source diffusion layer 71 c in the second line contactregion 70.

[0034] Referring now to FIG. 5, a self-aligned contact etch processusing the self-aligned contact mask 100 is implemented to form aplurality of self-aligned contact holes. After the self-aligned contactmask 100 is removed, the plurality of the self-aligned contact holes arefilled with a conductive material to form the plurality of the linecontact patterns 500 a, 500 b, 700 a and 700 b, thus completing the testpattern for measuring a contact resistance of the present invention.

[0035] In the above, the plurality of the line contact patterns 500 a,500 b, 700 a and 700 b are isolated/positioned in each of the first andsecond line contact regions 50 and 70. The first line contact pattern500 a for electrically connecting a source diffusion layer (not shown)and the first source diffusion layer 51 a, and the second line contactpattern 500 b for electrically connecting the second and third sourcediffusion layers 51 b and 51 c are isolated/positioned in the first linecontact region 50. Also, the first line contact pattern 700 a forelectrically connecting the first and second source diffusion layers 71a and 71 b, and the second line contact pattern 700 b for electricallyconnecting the third source diffusion layer 71 c and a source diffusionlayer (not shown) are isolated/positioned in the second line contactregion 70.

[0036] A process of manufacturing the test pattern for measuring acontact resistance or the present invention is performed based on adesign rule of a method of manufacturing an actual device for which atest pattern for measurement will be used

[0037] A method of measuring the contact resistance using the testpattern for measuring the contact resistance of the present inventionwill be described in short as follows.

[0038] Assuming that the number of a contact is “N”, the resistance ofthe line contact pattern is “Rm”, the resistance of the contact is “Rc”,the resistance of the diffusion layer is “Rd”, the voltage applied tomeasure the resistance is “V” and the current measured against thevoltage “V” is “I”, the total resistance “RT” and the contact resistance“Rc” can be found by the following [Equation 1].

RT=Nx(+Rc+Rd)=V/I  [Equation1]

RC=V/(N×I)−Rm−Rd≈V/(N×I)−Rd

[0039]FIG. 6˜FIG. 8 are cross sectional views for describing a method ofmanufacturing a test pattern for measuring a contact resistance in FIG.2 according to a second embodiment of the present invention, whereinFIG. 6a, FIG. 7a and FIG. 8a illustrate layouts; FIG. 6b, FIG. 7b andFIG. 8b are cross-sectional view of the test pattern taken along linesB-B in FIG. 6a, FIG. 7a and FIG. 8a, respectively; FIG. 6c, FIG. 7c andFIG. 8c are cross-sectional view of the test pattern taken along linesC-C in FIG. 6a, FIG. 7a and FIG. 8a, respectively; and FIG. 6d, FIG. 7dand FIG. 8d are cross-sectional view of the test pattern taken alonglines D-D in FIG. 6a, FIG. 7a and FIG. 8a, respectively.

[0040] Referring now to FIG. 6, the plurality of the device isolationfilms 30 are formed in the test wafer 20 to define the plurality of theactive regions 40. The first line contact region 50 and the second linecontact region 70 are defined so that the line contact region can form apair between the word line regions 60. A threshold voltage ionimplantation process is performed to form the threshold voltage ionimplantation regions 610 a, 610 b and 610 c in each of the activeregions 40 in the word line region 60.

[0041] Referring now to FIG. 7, the word line 61 is formed in the wordline region 60 in which the plurality of the threshold voltage ionimplantation regions 610 a, 610 b and 610 c are formed. An impurity ionimplantation process is performed to form the source diffusion layers 51a, 51 b and 51 c in each of the plurality of the active regions 40 ofthe first line contact region 50 and the source diffusion layers 71 a,71 b and 71 c in each of the plurality of the active regions 40 in thesecond line contact region 70. Then, the insulating film spacer 80surrounding the word line 61 is formed by a deposition process of theinsulating film and an etch process of the spacer. Next, the insulatinglayer 90 the surface of which is flattened is formed on the entirestructure including the word line 61. Next, the self-aligned contactmask 100 is formed on the insulating layer 90.

[0042] In the above, the first line contact region 50 and the secondline contact region 70 are electrically connected by the plurality ofthe threshold voltage ion implantation regions 610 a, 610 b and 610 c.More particularly, the first source diffusion layers 51 a and 71 a inthe first and second line contact regions 50 and 70 are electricallyconnected by the first threshold voltage ion implantation region 610 ain the word line region 60, the second source diffusion layers 51 b and71 b in the first and second line contact regions 50 and 70 areelectrically connected by the second threshold voltage ion implantationregion 610 b in the word line region 60, and the third source diffusionlayers 51 c and 71 c in the first and second line contact regions 50 and70 are electrically connected by the third threshold voltage ionimplantation region 610 c in the word line region 60. In order for themto be electrically connected, a voltage must be applied to the word line60 to form a channel.

[0043] The self-aligned contact mask 100 is formed to cover an upperportion of the word line 61, an upper portion of a portion of the deviceisolation film 30 between the first source diffusion layer 51 a and thesecond source diffusion layer 51 b in the first line contact region 50,and an upper portion of a portion of the device isolation film 30between the second source diffusion layer 71 b and the third sourcediffusion layer 71 c in the second line contact region 70.

[0044] Referring now to FIG. 8, a self-aligned contact etch processusing the self-aligned contact mask 100 is performed to form theplurality of the self-aligned contact holes. After the self-alignedcontact mask 100 is removed, the plurality of the self-aligned contactholes are filled with a conductive material to form the plurality of theline contact patterns 500 a, 500 b, 700 a and 700 b, thus completing thetest pattern for measuring a contact resistance of the presentinvention.

[0045] In the above, the plurality of the line contact patterns 500 a,500 b, 700 a and 700 b are isolated/positioned in each of the first andsecond line contact regions 50 and 70. The first line contact pattern500 a for electrically connecting a source diffusion layer (not shown)and the first source diffusion layer 51 a, and the second line contactpattern 500 b for electrically connecting the second and third sourcediffusion layers 51 b and 51 c are isolated/positioned in the first linecontact region 50. Also, the first line contact pattern 700 a forelectrically connecting the first and second source diffusion layers 71a and 71 b, and the second line contact pattern 700 b for electricallyconnecting the third source diffusion layer 71 c and the sourcediffusion layer (not shown) are isolated/positioned in the second linecontact region 70.

[0046] A process of manufacturing the test pattern for measuring acontact resistance or the present invention is performed based on adesign rule of a method of manufacturing an actual device for which atest pattern for measurement will be used

[0047] The first and second embodiment of the present invention relateto a method of manufacturing a test pattern for measuring a contactresistance. The test pattern for measuring a contact resistancemanufactured by the first embodiment and the test pattern for measuringa contact resistance manufactured by the second embodiment are same instructure to the test pattern for measuring a contact resistance shownin FIG. 2. in the test pattern for measuring a contact resistancemanufactured by the second embodiment, however, a voltage must beapplied the word line 61 between the first and second line contactregions 50 and 70 in order to measure the contact resistance and avoltage must not be applied to the word line 61 outside the first andsecond line contact regions 50 and 70.

[0048] As mentioned above, the present invention has outstandingadvantages that it can easily measure a contact resistance suitable fora semiconductor device and diagnose in advance a problem that may occurin an actual device based on the measured contact resistance data beforean actual process for manufacturing the device using a self-aligned linecontact is performed. Further, the present invention can not onlyconsider a new method of reducing the contact resistance but alsodetermine to what extent the cell area can be reduced. In addition, thepresent invention can not only increase the throughput of the device butalso reduce unnecessary time and cost by preventing in advance defectivedevices.

[0049] The present invention has been described with reference to aparticular embodiment in connection with a particular application. Thosehaving ordinary skill in the art and access to the teachings of thepresent invention will recognize additional modifications andapplications within the scope thereof.

[0050] It is therefore intended by the appended claims to cover any andall such applications, modifications, and embodiments within the scopeof the present invention.

What is claimed is:
 1. A test pattern for measuring a contactresistance, comprising: a test wafer in which a plurality of deviceisolation films are formed to define a plurality of active regions; aplurality of interconnection diffusion layer formed in a word lineregion crossing the plurality of the device isolation films and theplurality of the active regions; a plurality of source diffusion layersformed in a first line contact region located at one side of said wordline region; a plurality of source diffusion layers formed in a secondline contact region located at the other side of said word line region;and a plurality of line contact pattern formed in said first and secondline contact regions, wherein said line contact pattern formed in saidfirst line contact region and said line contact pattern formed in saidsecond line contact region are alternately positioned and whereincurrent for measuring a resistance flows along said first line contactregion and said second line contact region between said word line in athree-dimensional manner.
 2. The test pattern for measuring a contactresistance as claimed in claim 1, wherein said word line region, saidfirst line contact region and said second line contact region arejuxta-positioned.
 3. The test pattern for measuring a contact resistanceas claimed in claim 1, wherein said source diffusion layer in said firstline contact region and said source diffusion layer in said second linecontact region are electrically connected by an interconnectiondiffusion layer in said word line region.
 4. The test pattern formeasuring a contact resistance as claimed in claim 1, wherein one of theplurality of the line contact patterns in said first line contact regionelectrically connects two of the plurality of the source diffusionlayers in said first line contact region and is isolated/positioned fromanother line contact pattern.
 5. The test pattern for measuring acontact resistance as claimed in claim 1, wherein one of the pluralityof the line contact patterns in said second line contact regionelectrically connects two of the plurality of the source diffusionlayers in said second line contact region and is isolated/positionedfrom another line contact pattern.
 6. A method of manufacturing a testpattern for measuring a contact resistance forming a plurality of deviceisolation films in a test wager to define a plurality of active regions;performing an impurity ion implantation process to simultaneously form asource diffusion layer in a plurality of active regions of a first linecontact region, an interconnection diffusion layer in a plurality ofactive regions of a word line and a source diffusion layer in aplurality of active regions of a second line contact region; forming aword line surrounded by an insulating film spacer in said word lineregion; forming an insulating layer the surface of which is flattened onthe entire structure including said word line; forming a self-alignedcontact mask on said insulating layer; and forming a plurality of linecontact patterns in said first and second line contact regions through aself-aligned contact process using said self-aligned contact mask,wherein said line contact pattern formed in said first line contactregion and said line contact pattern formed in said second line contactregion are alternately positioned and current for measuring a resistanceflows along said first line contact region and said second line contactregion between said word line in a three-dimensional manner.
 7. Themethod of manufacturing a test pattern for measuring a contactresistance as claimed in claim 6, wherein said word line region, saidfirst line contact region and said second line contact region arejuxta-positioned crossing the plurality of the device isolation filmsand the plurality of the active regions.
 8. The method of manufacturinga test pattern for measuring a contact resistance as claimed in claim 6,wherein said source diffusion layer in said first line contact regionand said source diffusion layer in said second line contact region areelectrically connected by an interconnection diffusion layer in saidword line region.
 9. The method of manufacturing a test pattern formeasuring a contact resistance as claimed in claim 6, wherein one of theplurality of the line contact patterns in said first line contact regionelectrically connects two of the plurality of the source diffusionlayers in said first line contact region and is isolated/positioned fromanother line contact pattern.
 10. The method of manufacturing a testpattern for measuring a contact resistance as claimed in claim 6,wherein one of the plurality of the line contact patterns in said secondline contact region electrically connects two of the plurality of thesource diffusion layers in said second line contact region and isisolated/positioned from another line contact pattern.
 11. The method ofmanufacturing a test pattern for measuring a contact resistance asclaimed in claim 6, wherein said self-aligned contact mask is formed tocover an upper portion of said word line, an upper portion of a portionof said device isolation film between said first source diffusion layerand said second source diffusion layer in said first line contactregion, and an upper portion of a portion of said device isolation filmbetween said second source diffusion layer and said third sourcediffusion layer in said second line contact region.
 12. A method ofmanufacturing a test pattern for measuring a contact resistance forminga plurality of device isolation films in a test wafer to define aplurality of active regions; performing a threshold voltage ionimplantation process to form a threshold voltage ion implantation regionin the plurality of the active regions in a word line region; forming aword line in said word line region; performing an impurity ionimplantation process to form a source diffusion layer in each of theplurality of the active regions of a first line contact region and asource diffusion layer in each of the plurality of the active regions ofa second line contact region; forming an insulating film spacersurrounding said word line; forming an insulating layer the surface ofwhich is flattened on the entire structure including said word line;forming a self-aligned contact mask on said insulating layer; andforming a plurality of line contact patterns in said first and secondline contact regions through a self-aligned contact process using theself-aligned contact mask, wherein said line contact pattern formed insaid first line contact region and said line contact pattern formed insaid second line contact region are alternately positioned and currentfor measuring a resistance flows along said first line contact regionand said second line contact region between said word line in athree-dimensional manner.
 13. The method of manufacturing a test patternfor measuring a contact resistance as claimed in claim 12, wherein saidword line region, said first line contact region and said second linecontact region are juxta-positioned crossing the plurality of the deviceisolation films and the plurality of the active regions.
 14. The methodof manufacturing a test pattern for measuring a contact resistance asclaimed in claim 12, wherein the source diffusion layer in the firstline contact region and the source diffusion layer in the second linecontact region are electrically connected by a channel formed in athreshold voltage ion implantation region by applying a voltage to theword line in said word line region.
 15. The method of manufacturing atest pattern for measuring a contact resistance as claimed in claim 12,wherein one of the plurality of the line contact patterns in said firstline contact region electrically connects two of the plurality of thesource diffusion layers in said first line contact region and isisolated/positioned from another line contact pattern.
 16. The method ofmanufacturing a test pattern for measuring a contact resistance asclaimed in claim 12, wherein one of the plurality of the line contactpatterns in said second line contact region electrically connects two ofthe plurality of the source diffusion layers in said second line contactregion and is isolated/positioned from another line contact pattern. 17.The method of manufacturing a test pattern for measuring a contactresistance as claimed in claim 12, wherein said self-aligned contactmask is formed to cover an upper portion of said word line, an upperportion of a portion of said device isolation film between said firstsource diffusion layer and said second source diffusion layer in saidfirst line contact region, and an upper portion of a portion of saiddevice isolation film between said second source diffusion layer andsaid third source diffusion layer in said second line contact region.